High Bandwidth Memory
Technology
HBM achieves higher bandwidth) than DDR4 or GDDR5 while using less power, and in a substantially smaller form factor. This is achieved by stacking up to eight DRAM dies) and an optional base die which can include buffer circuitry and test logic. The stack is often connected to the memory controller on a GPU or CPU through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack the dies are vertically interconnected by through-silicon vias (TSVs) and microbumps. The HBM technology is similar in principle but incompatible with the Hybrid Memory Cube (HMC) interface developed by Micron Technology.
Technology
The larger number of connections to the memory, relative to DDR4 or GDDR5, required a new method of connecting the HBM memory to the GPU (or other processor). AMD and Nvidia have both used purpose-built silicon chips, called interposers, to connect the memory and GPU. This interposer has the added advantage of requiring the memory and processor to be physically close, decreasing memory paths. However, as semiconductor device fabrication is significantly more expensive than printed circuit board manufacture, this adds cost to the final product.
Technology
• HBM DRAM die • HBM controller die • HBM memory on an AMD Radeon R9 Nano graphics card's GPU package
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